| Source: Breker Verification Systems
- Brings Advocacy for the adoption of RISC-V processors and processor verification tool standards
- Leverages broad experience in EDA business strategy, marketing and sales
SAN JOSE, Calif., March 05, 2026 (GLOBE NEWSWIRE) — Breker Verification Systems today named Larry Lapides, former Synopsys Executive Director of RISC-V Tools Business Development, to its Advisory Board.
In making today’s announcement, David Kelf, Breker’s CEO, noted that Lapides has been a tireless advocate for the adoption of RISC-V processors and the urgent need for RISC-V processor verification tool standards. “Larry’s RISC-V knowledge and his ties to the RISC-V community are welcome additions to Breker and our advisory board.”
“Breker sits at the forefront in the development of commercial processor verification solutions and is a valued member of the RISC-V community,” remarks Lapides. “It will be a pleasure to work with Breker to move this important effort forward.”
Larry Lapides Biography
Lapides joined Synopsys through the acquisition of Imperas Software, where he was Vice President of Worldwide Sales and Marketing. He previously ran worldwide sales at EDA companies including Verisity Design and has more than 30 years in software tools and EDA, plus time spent in infrared systems engineering.
Lapides holds a Bachelor of Arts degree in Physics from UC Berkeley, a Master of Science degree in Applied Physics from Cornell University and an MBA from Clark University in Worcester, Mass.
About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.
Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.
For more information, contact:
Nanette Collins
Public Relations for Breker Verification Systems
nanette@nvc.com
